This application is related to Korean Application No. 2000-21667, filed Apr. 24, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices, and more particularly to methods for fabricating semiconductor devices having plug contacts and upper interconnections on a processing substrate.
As the horizontal dimensions continue to decrease, accompanying with an increasing integrated circuit density, the aspect ratio (depth to wide) increases and it becomes increasingly difficult to etch reliable contact holes. It is, therefore, important to provide a technique to fill a narrower hole with conductive materials.
On the other hand, the topological width of contacts or interconnections is decreased in order to increase the density of the integrated circuit. However, as there are technical limits such as a resolution of an exposure device, it is difficult to remarkably reduce critical dimension (CD) in processes for a semiconductor device. Besides, an alignment margin in the exposure process is reduced due to micronized elements.
With respect to a smaller margin in aligning an exposure pattern, a damascene process can be used where plug contacts are connected with interconnections on a right junction. The damascene method for DRAMs employing a capacitor on bit line (COB) structure is disclosed in Japanese publication No. 10178160A. It may be possible to improve processing margins in forming lines or connections by means of the damascene method together with a self-alignment technique.
Despite the advanced processing techniques, a more accelerated integration rate for a semiconductor memory device causes new demands for upgrading manufacturing technologies adaptable thereto, arising from the resolution and alignment in the exposure process, and shaping plug contacts.
In case that the widths of a bit line and a contact hole are designed to be 100 xcexcm and over 90 xcexcm, respectively, and a limitation of an exposure alignment is over 50 xcexcm, even though the bit line is within these limitations, there is no guarantee that the bit line will cover the plug contact in the contact hole completely. In another case that the widths of a bit line and a contact hole are 80 xcexcm and at least over 100 xcexcm, respectively, it is impossible that the bit line completely covers the plug contact in a junction.
Under those conditions, the damascene process disclosed in the Japanese publication No. 10178160A may not be useful. In other words, in shaping self-aligned bit lines, a gap between storage electrode plug contacts and bit lines becomes small (as much as a thickness of a spacer,) and thereby a parasitic capacitance between the plug contacts and the bit lines increases. Therefore, the bit lines would typically not be formed with a sufficient margin as well as the advantage of the damascene process. In known manners except the damascene process, upper interconnections may not cover a region of the contacts.
A general method of fabricating bit lines concurrently with plug contacts is now described, referring to FIG. 1. A metal interconnection 25 is aligned to cover a plug contact 23 and a barrier layer pattern 21 sufficiently, as shown in FIG. 1. Accordingly, the portions of the plug contact 23 and the barrier layer pattern 21 are recessed.
The barrier layer pattern 21 is recessed by etching a barrier layer to form a bit line. First, in a process of etching a metal layer for making the metal interconnection 25, a portion not covered with an etching mask is consumed to shape a concave portion. The concave portion caused from over-etching is increasingly attacked, so that a portion full of plug contacts is recessed to expose the barrier layer on a sidewall thereof. Consequently, the barrier layer can be attacked in a process of forming the barrier layer pattern 21 by removing the barrier layer stacked on an intermediate insulating layer.
Furthermore, the etching of the barrier layer pattern 21 is advanced along the attacked portion when removing residues on the intermediate insulating layer using an over etching of the barrier layer, and thereby the barrier layer extending between the plug contact and the intermediate insulating layer may be mostly removed.
As the damage is increased, the amounts of fluorine elements, supplied as an etching gas or generated in the etching process, that permeate into an interface between a silicon layer and the barrier layer under the plug contact are increased. And the permeated fluorine elements form a nonconductor layer such as SiF4 on the interface. Otherwise, the fluorine elements may be latent for a while, and react with the barrier layer of the interface by means of a following heating process. In this case, the reaction forms the nonconductor and makes the interface separate, so that the semiconductor elements are difficult to operate normally in addition to having increased contact resistance.
According to an aspect of the present invention, there is provided a semiconductor device formed of an intermediate insulating layer, formed on a semiconductor substrate, having a contact hole in which a region of the substrate is exposed, and a lower barrier layer covering a sidewall and bottom of the contact hole. On the barrier layer, a plug contact being filled in the contact hole is provided, and a predetermined portion is protruded above the top surface of the intermediate insulating layer. Further, the protruded portion, at least a part, of the plug contact is covered with an upper barrier layer pattern which is covered with a metal interconnection thereon. A spacer, made of the same material as the upper barrier layer pattern, is in a sidewall of the protruded portion of the plug contact.
A predetermined region of the semiconductor substrate exposed through the contact hole is mostly a dopant region which is doped over a silicon substrate or a polysilicon pad. An ohmic metal layer may be intervened between the lower barrier layer pattern and the sidewall and bottom of the contact hole. The lower barrier layer pattern and the ohmic metal layer pattern are composed of a titanium nitride (TiN) and a titanium (Ti), respectively. The plug contact generally uses tungsten (W). The upper layer pattern may use TiN, and the upper metal interconnection may use W or copper (Cu). Further, the present invention is adaptable to fabricate bit line contacts and bit lines of DRAM devices employing a capacitor on bit line (COB) structure.
According to another aspect of this invention, a method for fabricating a semiconductor device begins by forming an intermediate insulating layer on a semiconductor substrate, and patterning to expose a predetermined region of the substrate. Thereafter, a lower barrier layer and a metal layer are sequentially deposited over an inner side of the contact hole.
In general, a method for depositing the layers includes the steps of depositing the lower barrier layer and the metal layer over an entire surface of the substrate, planarizing the metal layer to form a plug contact, and etching an entire surface of the lower barrier layer to expose a top surface of the intermediate insulating layer. Here, a recessed lower barrier layer pattern may be formed to expose an upper sidewall of the contact hole by over etching. The intermediate insulating layer is to be recessed by an entire surface etching over the layer, so that an upper portion of the plug contact becomes higher than the top surface of the intermediate insulating layer. And then, the upper barrier layer pattern which covers at least a part of the protruded portion of the plug contact and a metal interconnection are formed by utilizing a method of depositing the upper barrier layer and the metal layer over the entire surface of the substrate, and etching the layers after forming a mask pattern.
To form the upper barrier layer pattern and the metal interconnection, the upper barrier layer and an interconnection metal layer are sequentially deposited after a portion of the plug contact is protruded. The interconnection metal layer and the upper barrier layer are sequentially etched by using a general patterning process.
If the plug contact uses tungsten (W), a method for the planarization employs the entire surface etching or a chemical mechanical polishing (CMP) method. When the lower barrier layer pattern enclosing the plug contact is recessed below the top surface of the intermediate insulating layer, it is preferable that the entire surface etching of the intermediate insulating layer is advanced to be the same level with the top surface of the lower barrier layer pattern. If the lower barrier layer pattern is not recessed, the entire surface etching of the intermediate insulating layer is advanced to be lower than the top surface of the lower barrier layer pattern.